1. Field of the Invention
The present invention relates to a multiple phase-locked loop (PLL) circuit having a function of preventing a deadlock.
The present application claims priority of Japanese Patent Application No. 2001-044337 filed on Feb. 20, 2001 which is hereby incorporated by reference.
2. Description of the Related Art
Generally, in a conventional multiple PLL circuit, as explained in detail later, an UP signal used to increase an oscillation frequency and a DN signal used to lower the oscillation frequency are output from a phase/frequency comparator adapted to detect a difference in phase between a reference signal and a feedback signal obtained by dividing a frequency of an oscillation signal output from a voltage controlling oscillator (VCO). Then, an error signal produced based on each of pulse widths of the UP signal and DN signal is output from a charge pumping circuit. A control signal being at a level corresponding to that of the error signal is output through a low pass filter (LPF), which controls the oscillation signal output from the voltage controlling oscillator to cause the oscillation frequency to match the frequency of the reference signal, thus causing the oscillation signal to be synchronized with the reference signal.
Hereinafter, configurations and operations of the conventional multiple PLL circuit will be described by referring to FIG. 9. As shown in FIG. 9, the conventional multiple PLL circuit chiefly includes a phase/frequency comparator (PFD) 1, a charge pumping (CP) circuit 2, a low pass filter (LPF) 3, a voltage controlling oscillator (VCO) 4, and a frequency divider (DIV) 5.
The PFD 1 compares a phase or a frequency of a signal input to an input terminal S1 with a phase or a frequency of another signal input to an input terminal S2 and, if the other signal input to the input terminal S2 lags the signal input to the input terminal S1 or if the frequency of the other signal input to the input terminal S2 is lower than that of the signal to the input terminal S1, outputs an UP signal being a pulse which falls by a rise of the signal input to the input terminal S1 and rises by a rise of the other signal input to the input terminal S2, to an output terminal xe2x80x9cuxe2x80x9d and further, if the other signal input to the input terminal S2 leads the signal input to the input terminal S1 or if the frequency of the other signal input to the input terminal S2 is higher than that of the signal input to the input terminal S1, outputs a DN signal being a pulse which rises by a rise of the other signal input to the input terminal S2 and falls by a rise of the signal input to the input terminal S1.
The CP circuit 2, by generating an error signal to be output from an output terminal xe2x80x9cexe2x80x9d in response to an UP signal input to an input terminal L1 and in response to a DN signal input to an input terminal L2, operates so as to cause a current to flow out from a power source through the output terminal xe2x80x9cexe2x80x9d or a current to flow to a ground from the output terminal xe2x80x9cexe2x80x9d. The LPF 3, by removing a high frequency component based on the flow-in and flow-out of currents contained in the error signal fed from the charge pumping circuit 2, generates a smoothed control signal. The VCO 4 generates an output clock signal a frequency of which changes to be high or low depending on whether a control voltage is large or small. The DIV 5 outputs a frequency-divided clock signal div.CLK obtained by dividing a frequency of an output clock signal VCO.CLK output from the VCO 4.
The conventional PFD 1, as shown in FIG. 10, includes inverters 1A, 1B, 1M, 1N, 1P, 1R to 1T, 1V to 1Y, NAND gates 1C to 1H, 1J, 1K, NOR gates 1L, 1Q, and 1U. Of them, the NAND gates 1D and 1E make up a first flip-flop and the NAND gates 1G and 1H make up a second flip-flop. Moreover, the NOR gate 1Q and the inverters 1R and 1S make up a reset circuit.
A reference clock signal ref.CLK input to the input terminal S1 is fed through the inverter 1A to the NAND gate IC. The NAND gate IC computes the NAND of the reference clock signal ref.CLK with a previous output signal and outputs a result of the computation to the NAND gate 1F. The NAND gate 1F computes the NAND of an output of the first flip-flop with an output from the NAND gate 1C and produces a signal 1a from a result of the computation. Moreover, the frequency-divided clock signal div.CLK output from the DIV 5 and input to the input terminal S2 is fed through the inverter 1B to the NAND gate 1J. The NAND gate 1J computes the NAND of the frequency-divided clock signal div.CLK with a previous output signal and outputs a result of the computation to the NAND gate 1K. The NAND gate 1K computes the NAND of an output from the second flip-flop with an output from the NAND gate 1J and produces a signal 1b from a result of the computation.
The signal 1a is a signal generated based on the reference clock signal ref.CLK and its duty ratio is fixed, while the signal 1b is a signal generated based on the frequency-divided clock signal div.CLK obtained by dividing the output clock signal VCO.CLK using the DIV 5 and its duty ratio changes depending on a phase difference between the frequency-divided clock signal div.CLK and reference clock signal ref.CLK.
The signal 1a is output to the NOR gate 1L. The NOR gate 1L computes the NOR of a reset signal fed from the reset circuit with the signal 1a and outputs a result of the computation to the inverter 1M. The inverter 1M inverts the output from the NOR gate 1L to produce an output signal. The output from the inverter 1M is input to the NAND gate 1C and is also output as an UP signal to output terminal xe2x80x9cuxe2x80x9d through inverters 1N and 1P.
Also, the signal 1b is output to the NOR gate 1U. The NOR gate 1U computes the NOR of the reset signal from the reset circuit with the signal 1b and outputs a result of the computation to the inverter 1V. The inverter 1V inverts the output from the NOR gate 1U to generate an output signal. The output signal from the inverter 1V is output to the NAND gate 1J and through the inverters 1W, 1X, and 1Y to an output terminal xe2x80x9cdxe2x80x9d as a DN signal.
A relation between the UP signal and DN signal is described below. That is, if the frequency-divided clock signal div. CLK to be input to the input terminal S2 lags the reference clock signal ref.CLK to be input to the input terminal S1 or if a frequency of the frequency-divided clock signal div.CLK to be input to the input terminal S2 is lower than that of the reference clock signal ref.CLK to be input to the input terminal S1, as shown in FIG. 11, during a period of time from a rise of the reference clock signal ref.CLK input to the input terminal S1 to a rise of the frequency-divided clock signal div.CLK input to the input terminal S2, the UP signal being a downward pulse as shown by being hatched in FIG. 11 is output to the output terminal xe2x80x9cuxe2x80x9d. During this period, no DN signal is output to the output terminal xe2x80x9cdxe2x80x9d.
Moreover, if the frequency-divided clock signal div. CLK to be input to the input terminal S2 leads the reference clock signal ref.CLK to be input to the input terminal S1 or if a frequency of the frequency-divided clock signal div. CLK to be input to the input terminal S2 is higher than that of the reference clock signal ref.CLK to be input to the input terminal S1, as shown in FIG. 12, during a period of time from a rise of the frequency-divided clock signal div.CLK input to the input terminal S2 to a rise of the reference clock signal ref.CLK input to the input terminal S1, the DN signal being an upward pulse as shown by being hatched in FIG. 12 is output to the output terminal xe2x80x9cdxe2x80x9d. During this period, no UP signal is output to the output terminal xe2x80x9cuxe2x80x9d.
The CP circuit 2, by generating an error signal in response to the UP signal or DN signal output from the PFD 1, charges or discharges the LPF 3. Hereinafter, configurations and operations of the CP circuit 2 are described below.
The conventional CP circuit 2, as shown in FIG. 13, includes a positive P-type MOS (Metal Oxide Semiconductor) FET (Field Effect Transistor) 2A and a negative N-type MOSFET 2B. In FIG. 13, the P-type MOSFET 2A, when the UP signal being the downward pulse is fed to the input terminal L1, is turned ON, causing a current to flow out from a power source VDD through the output terminal xe2x80x9cexe2x80x9d. The N-type MOSFET 2B, when the DN signal being the upward pulse is fed to the input terminal L2, is turned ON, causing a current to flow in a ground through the output terminal xe2x80x9cexe2x80x9d.
At this time, in the CP circuit 2, a current source I1 to determine a value of a current flowing out through the P-type MOSFET 2A and a current source I2 to determine a value of a current flowing in through the N-type MOSFET 2B are configured so that values of currents flowing through both the current sources I1 and I2 are equal to each other. Hereafter, an output signal from the output terminal xe2x80x9cexe2x80x9d of the CP circuit 2 is called an xe2x80x9cerror signalxe2x80x9d.
The conventional LPF 3, as shown in FIG. 14, is so configured that a serial circuit made up of a resistor 3A and a first capacitor 3B both being in series connected and a second capacitor 3C are connected in parallel between the terminal for receiving the error signal and the ground and operates so as to remove high frequency components contained in the error signal fed from the CP circuit 2 and to allow low frequency components only to pass. This can avoid a sharp change in a voltage contained in the error signal fed from the CP circuit 2 and causes a smoothed control voltage to be output to the VCO 4.
Next, operations of the conventional PLL circuit will be explained. The VCO 4 outputs an output clock signal VCO.CLK having a frequency corresponding to the control voltage. The DIV 5 divides a frequency of the output clock signal VCO.CLK and outputs the frequency-divided clock signal div.CLK. The PFD 1 compares a phase of the reference clock signal ref.CLK with a phase of the frequency-divided clock signal div.CLK fed from the DIV 5 and outputs either of the UP signal or DN signal based on a difference in the frequency or in the phase between the reference clock signal ref.CLK and the frequency-divided clock signal div.CLK. The CP circuit 2 outputs the error signal based on the UP signal and the DN signal, which causes the control signal to be fed to the VCO 4 through the LPF 3 and causes the VCO 4 to change the frequency of the output clock signal VCO.CLK based on the control signal. This cyclical feedback control enables a frequency and a phase of the output clock signal VCO.CLK from the VCO 4 to match the reference clock signal ref.CTK and causes the output clock signal to be synchronized with the reference clock signal ref.CLK.
At this point, since an amount of a charge current to flow into the LPF 3 from the power source VDD through the P-type MOSFET 2A based on the UP signal, is equal to that of a discharge current to flow out from the LPF 3 to the ground through the N-type MOSFET 2B based on the DN signal, the control on the control signal fed to the VCO 4 used to control the frequency of the output clock signal VCO.CLK is equally exerted regardless of whether the frequency increases or decreases.
FIG. 15 is a timing chart explaining operations of the conventional multiple PLL circuit. In FIG. 15, a state of synchronization of signals in normal operation in a case of a frequency division rate being 8 is shown, in which the frequency-divided signal div.CLK, which is obtained by dividing the output clock signal VCO.CLK from the VCO 4 by eight in the DIV 5, is in synchronization with the reference clock signal ref.CLK.
When a frequency of the reference clock signal ref.CLK increases, the output clock signal VCO.CLK from the VCO 4 also increases. However, if the frequency of the reference clock signal ref.CLK increases abnormally due to some reasons, the frequency of the output clock signal VCO.CLK also increases abnormally. If the frequency increases so much that the DIV 5 cannot be operated, the DIV 5 does not implement its function and no further frequency-divided signal div.CLK is produced. In such the state, since the PFD 4 continues outputting the UP signal, the frequency of the output clock signal VCO.CLK from the VCO 4 increases to an extreme in the end. In this case, a negative feedback loop of the multiple PLL circuit is interrupted and ever if the frequency of the reference clock signal ref.CLK is restored to its original level, the frequency of the output clock signal VCO.CLK is still kept at the extreme level and, therefore, the multiple PLL circuit is not restored to its normal operations and falls into a deadlock state.
FIG. 16 is a timing chart explaining how the conventional multiple PLL circuit falls into a deadlock state. Operations in which the PLL circuit falls into the deadlock state will be explained by comparing them with those in the timing chart showing normal operations.
In FIG. 16, a state in which the frequency of the reference clock signal ref.CLK has increased due to some reasons is shown. It is also shown that the frequency of the output clock signal VCO.CLK from the VCO 4 increases at the same time and, as a result, the period of outputting the UP signal from the PFD 1 becomes longer gradually (see the left half portion in FIG. 16). In FIG. 16, a period shown by being hatched out of the period during which the UP signal is being output represents a period during which the LPF 3 is being charged in response to the error signal fed from the CP circuit 2. At this point, no DN signal from the PFD 1 is being output. Now, since the frequency of the reference clock signal ref.CLK is higher than that of the frequency-divided clock signal div.CLK, the multiple PLL circuit is in a state of starting to increase the frequency of the output clock signal VCO.CLK.
As the period of outputting the UP signal becomes longer, the frequency of the output clock signal VCO.CLK from the VCO 4 increases. However, if the frequency of the output clock signal VCO.CLK increases beyond a specified limit, the DIV 5 cannot catch up with the increase and stops operation in the end and, as a result, the frequency-divided clock signal div.CLK is not output, which means that there is no edge of a pulse to be compared by the PFD 1 and which causes the UP signal to be continuously output (see the right half portion in FIG. 16). Therefore, since the frequency of the output clock signal VCO.CLK from the VCO 4 increases to an extreme and the negative feedback loop is interrupted at the DIV 5, the multiple PLL circuit falls into a uncontrollable state and into a deadlock state.
Thus, if the oscillation frequency of a signal output from the VCO 4 increases abnormally, since a frequency dividing circuit adapted to divide the oscillation frequency of the signal output from the VCO 4 falls in an inoperable state, causing no further input of a feedback signal to the PFD 1, the multiple PLL circuit falls into a deadlock state and its control is not restored to its normal state. It is therefore desirous that, if the PLL circuit falls into a deadlock state, by detecting the deadlock state by some means and by exerting control so as to clear the deadlock state, it can be automatically restored to its normal operation.
A multiple PLL circuit having such the function of clearing the deadlock state is disclosed in, for example, Japanese Patent Application Laid-open No. Hei 11-122102. In the disclosed conventional multiple PLL circuit, a flip-flop is provided which is set by a rise of an output signal from a dividing circuit adapted to divide a frequency of a reference signal and is reset by a signal having detected a change of a feedback signal output from a logic circuit adapted to divide an oscillation frequency of a signal output from a VCO. When a change of the feedback signal is detected during a period of time from a rise to another rise of the output signal from the frequency dividing circuit, an output signal from the flip-flop goes low, which causes a control signal controlling circuit to transfer an UP signal and DN signal output from a phase comparator, as they are, to a charge pumping circuit to restore the PLL circuit to its normal operation.
On the other hand, when the PLL circuit falls in a deadlock state in which a feedback signal is not output, a change of the feedback signal is not detected and therefore an output signal from the flip-flop goes high and, as a result, both the UP signal and DN signal output from the control signal controlling circuit go high. This causes an error signal output from a charge pumping circuit to lower a voltage level of a control signal output from the LPF and, as a result, an oscillation frequency of a signal from the VCO is lowered, thus restoring the PLL circuit to its normal operation.
However, the conventional multiple PLL circuit having the deadlock clearing function has a problem. That is, in the flip-flop employed in the conventional PLL circuit which is adapted to generate a control signal for the control signal controlling circuit, periodical setting and resetting are repeated in a normal operation state, however, timing with which the resetting is performed is not so simple. In other words, there is a possibility that critical timing exists with which an output voltage of the low pass filter is accidentally lowered even in a state of normal operations of the multiple PLL circuit, depending on the oscillation frequency of the signal from the VCO.
Thus, in the conventional PLL circuit having the deadlock preventing mechanism, since the deadlock clearing circuit is constructed of an element having an architecture being totally different from a mechanism causing the deadlock there is a risk that normal operations of the multiple PLL circuit itself are disturbed.
In view of the above, it is an object of the present invention to provide a multiple phase-locked loop circuit capable of starting operations of a deadlock preventing mechanism which is triggered by an interruption of a frequency-divided clock output from a voltage controlling oscillator caused by an inoperable state of a frequency divider and of reliably preventing occurrence of a deadlock state without disturbing normal operations while no deadlock has occurred by using a circuit in which an operation of a phase/frequency comparator being one of causes for the occurrence of the deadlock is utilized in a reverse manner, for preventing the deadlock.
According to a first aspect of the present invention, there is provided a multiple phase-locked loop circuit including:
a first phase/frequency comparing unit to compare a phase or a frequency of a reference clock with a phase or a frequency of a first frequency-divided clock and to output an UP signal or a first DN signal depending on whether the first frequency-divided clock lags or leads the reference clock or whether a frequency of the first frequency-divided clock is lower or higher than that of the reference clock;
a charge pumping unit to generate an error signal by causing a current to flow out, in response to the UP signal, and by causing a current to flow in, in response to the first DN signal;
a low pass filter to smooth the error signal and to output the smoothed error signal as a control voltage;
a voltage control oscillating unit to generate an output clock whose frequency changes to be high or low depending on whether the control voltage is high or low;
a first frequency-divided unit to output the first frequency-divided clock obtained by dividing the frequency of the output clock at a specified frequency division rate;
a second phase/frequency comparing unit to compare a phase or a frequency of the first frequency-divided clock with a phase or a frequency of the reference clock or of a clock having a frequency being lower than that of the reference clock and, when the first frequency-divided clock lags the frequency clock or the clock having the frequency being lower than that of the reference clock or a frequency of the first frequency-divided clock is lower than that of the reference clock or of the clock having the frequency being lower than that of the reference clock, to output a second DN signal; and
wherein the multiple phase-locked loop circuit is able to get out of a deadlock state by using the second DN signal.
In the foregoing, a preferable mode is one that wherein includes a second frequency-dividing unit to output a second frequency-divided clock obtained by dividing the reference clock at a specified frequency division rate and
wherein the second phase/frequency comparing unit compares a phase of the first frequency-divided clock with a phase of the second frequency-divided clock and, when a frequency of the first frequency-divided clock is lower than that of the second frequency-divided clock, outputs the second DN signal.
According to a second aspect of the present invention, there is provided a multiple phase-locked loop circuit including
a first phase/frequency comparing unit to compare a phase or a frequency of a reference clock with a phase or a frequency of a first frequency-divided clock and to output an UP signal or a first DN signal depending on whether the first frequency-divided clock lags or leads the reference clock or whether a frequency of the first frequency-divided clock is lower or higher than that of the reference clock;
a second phase/frequency comparing unit to compare a phase or a frequency of the first frequency-divided clock with a phase or a frequency of the second frequency-divided clock and, when the first frequency-divided clock lags the second frequency-divided clock or when a frequency of the first frequency-divided clock is lower than that of the second frequency-divided clock, to output a second DN signal;
a charge pumping unit to generate an error signal by causing a current to flow out in response to the UP signal, by causing a same amount of currents as that of the current flowing out in response to the UP signal to flow out in response to the first DN signal and by causing an amount of currents being greater than that of currents flowing in response to the UP signal or in response to the first DN signal to flow in, in response to the second DN signal;
a low pass filter to smooth the error signal and to output the smoothed error signal as a control voltage;
a voltage control oscillating unit to generate an output clock whose frequency changes to be high or low depending on whether the control voltage as high or low;
a first frequency-divided unit to output the first frequency-divided clock obtained by dividing the frequency of the output clock at a specified frequency division rate; and
a second frequency-divided unit to output the second frequency-divided clock obtained by dividing the frequency of the reference clock at a specified frequency division rate.
According to a third aspect of the present invention, there is provided a multiple phase-locked loop circuit including:
a first phase/frequency comparing unit to compare a phase or a frequency of a reference clock with a phase or a frequency of a frequency-divided clock and to output an UP signal or a first DN signal depending on whether a first frequency-divided clock lags or leads the reference clock or whether a frequency of the first frequency-divided clock is lower or higher than that of the reference clock;
a second phase/frequency comparing unit to compare a phase or a frequency of the frequency-divided clock with a phase or a frequency of a reference clock and, when the frequency-divided clock lags the reference clock or when a frequency of the frequency-divided clock is lower than that of the reference clock, to output a second DN signal;
a charge pumping unit to generate an error signal by causing a current to flow out in response to the UP signal, by causing a same amount of currents as that of the current flowing out in response to the UP signal to flow in, in response to the first DN signal and by causing an amount of currents being greater than that of the current flowing in response to the UP signal or in response to the first DN signal to flow in, in response to the second DN signal and to stop the current flowing in based on the second DN signal, in response to a control voltage detecting signal;
a low pass filter to smooth the error signal and to output the smoothed error signal as a control signal;
a voltage control oscillating unit to generate an output clock whose frequency changes to be high or low depending on whether the control voltage is high or low;
a frequency-divided unit to output the frequency-divided clock obtained by dividing the frequency of the output clock at a specified frequency division rate; and
a control voltage detecting unit to output the control voltage detecting signal when the control voltage drops below a specified voltage level.
In the foregoing, a preferable mode is one wherein the control voltage detecting unit performs a hysteresis operation which outputs the control voltage detecting signal when the control voltage has dropped below the specified voltage level and thereafter keeps a state of outputting the control voltage detecting signal and which stops outputting of the control voltage detecting signal when the control voltage has risen and exceeded a second specified voltage level.
Also, a preferable mode is one wherein the charge pumping unit is so configured so as to stop, when the second DN signal is output, a current flowing out in response to the UP signal.
Furthermore, a preferable mode is one wherein the low pass filter is so configured that a serial circuit made up of a resistor and a first capacitor being in series connected and a second capacitor are connected in parallel between a terminal for receiving the error signal and a ground.
With the above configurations, a first frequency-divided clock is generated by dividing a frequency of an output clock signal output from the control voltage oscillating unit and a second frequency-divided clock is generated by dividing a frequency of a reference clock. By using the first phase/frequency comparing unit, a phase or a frequency of the first frequency-divided clock is compared with a phase or a frequency of the reference clock and an UP signal or a first DN signal is output depending on whether the first frequency-divided clock lags or leads the reference clock or whether a frequency of the first frequency-divided clock is lower or higher than that of the reference clock. Moreover, by using the second phase/frequency comparing unit, a phase or a frequency of the first frequency-divided clock is compared with a phase or a frequency of the second frequency-divided clock and if the first frequency-divided clock lags the second frequency-divided clock or the frequency of the first frequency-divided clock is lower than that of the second frequency-divided clock, a second DN signal is output. By using the charge pumping unit, an error signal is generated by causing a current to flow out in response to the UP signal, by causing the same amount of currents as that of the current flown out in response to the UP signal to flow in, in response to the first DN signal and by causing an amount of currents being greater than that of the current flowing in response to the UP signal or in response to the first DN signal to flow in, in response to the second DN signal. By using the low pass filter, the error signal is smoothed and the smoothed signal is output as a control signal and, by using the voltage control oscillating unit, an output clock is generated, the frequency of which changes to be high or low depending on which the control voltage is large or small. Therefore, even if the multiple PLL circuit falls into a deadlock state due to no outputting of the first frequency divided clock caused by an abnormal increase of the frequency of the output clock, the frequency of the output clock is rapidly lowered, thus enabling the multiple PLL circuit to get out of the deadlock state.
With another configuration as above, a frequency-divided clock is generated by dividing a frequency of an output clock signal output from the voltage control oscillating unit. By using the first phase/frequency comparing unit, a phase or a frequency of the frequency-divided clock is compared with a phase or a frequency of the reference clock and an UP signal or a first DN signal is output depending on whether the frequency-divided clock lags or leads the reference clock or whether the frequency of the frequency-divided clock is lower or higher than that of the reference clock. Similarly, by using the second phase/frequency comparing unit, a phase or a frequency of the frequency-divided clock is compared with a phase or a frequency of the reference clock and if the frequency-divided clock lags the reference clock or if the frequency of the frequency-divided clock is lower than that of the reference clock, a second DN signal is output. Moreover, By using the charge pumping unit, an error signal is generated by causing a current to flow out in response to the UP signal, by causing the same amount of currents as that of the current flown out in response to the UP signal to flow in, in response to the first DN signal and by causing an amount of currents being greater than that of the current flowing in response to the UP signal or in response to the first DN signal to flow in, in response to the second DN signal. By using the low pass filter, the error signal is smoothed and the smoothed signal is output as a control signal and, by using the voltage control oscillating unit, an output clock is generated, the frequency of which changes to be high or low depending on which the control voltage is large or small. Furthermore, by using the control voltage detecting unit, a control voltage detecting signal is output when a control voltage has dropped below a specified voltage level and, by using the charge pumping unit, flow-in of the currents based on the second DN signal is stopped in response to the control voltage detecting signal. Therefore, even if no frequency divider to divide a frequency of the reference clock is provided on an input side of the second phase/frequency comparing unit, the multiple PLL circuit can operate normally as the multiple PLL circuit having a deadlock preventing function.